1. Field of the Invention
The present invention relates to an absolute value arithmetic circuit for computing the absolute value of a difference between two digital numeral values in a digital signal processor (DSP), a microprocessor, a microcomputer or the like.
2. Description of the Related Art
Heretofore, technology in the above-mentioned field is disclosed in the "Study of Absolute Value Computing System" issued at the 1986th national conference of the communication branch of the Institute of Electronics Communication Engineers, 1-46. The arrangement disclosed in this literature will be explained below.
FIGS. 2a to 2d are circuit block diagrams illustrating conventional absolute value arithmetic circuits. FIG. 2a shows a parallel-type circuit, FIG. 2b shows a series-type circuit, FIG. 2c shows an input register type circuit, and FIG. 2d shows an output feed-back type circuit.
In FIG. 2a, the parallel type absolute value computing circuit 10 is composed of two subtractors connected in parallel with each other, and a selector 13.
The subtractors 11 and 12 calculate differences between two input signals Sin1 and Sin2, that is (Sin1-Sin2) and (Sin2-Sin1), respectively. The selector 13 selects and outputs a positive result of the calculation. In this arrangement, for example, the subtractor 11 outputs the most significant bit denoted hereinbelow as "MSB") or the sign digit bit as a control input signal Sc to control the selector 13.
The series type absolute value arithmetic circuit 20 shown in FIG. 2b is composed of a subtractor 21, a sign inverter 22 connected in series to the subtractor 21 and a selector 23. The sign inverter 22 is composed of a 2's complement circuit including an inverting circuit and an adder.
In this absolute value arithmetic circuit 20, the subtractor 21 calculates a difference between two input signals Sin1 and Sin2, that is, (Sin1-Sin2). In accordance with a resultant signal of the computation, if the value is positive the selector 23 outputs the value as it is, but if the value is negative, it selects and delivers an output from the sign inverter 22 by which the value is inverted and is subjected to 2's complement computation by addition. In this arrangement, for example, the subtractor 21 outputs the MSB which is used as a control input signal Sc to the selector 23.
In FIG. 2c, the input register type absolute value arithmetic circuit 30 shown in FIG. 2c, is composed of registers 31 and 32, a selector 33, and a subtractor 34.
In this absolute value arithmetic circuit 30, two input signals Sin1 and Sin2 are stored in the registers 31 and 32, respectively, and the subtractor 34 calculates a difference between the two input signals Sin1 and Sin2, that is, (Sin1-Sin2). If the result of the calculation is a positive value, the selector 33 outputs the value as it is. However, if it is negative, the selector 33 exchanges the signals stored in the registers 31 and 32. The subtractor 34 again subtracts the thus replaced signals and delivers the result of the subtraction during the next clock cycle. In this arrangement, for example, the MSB of an output from the subtractor 34 is used as a control input signal Sc to the selector 33.
The output feed-back type absolute value arithmetic circuit 40, as shown in FIG. 2d, is composed of a subtractor 41, a register 42, and a selector 43.
In this absolute value computing circuit 40, the subtractor 41 calculates a difference between two input signals Sin1 and Sin2, that is, (Sin1-Sin2), and if the difference is positive, the value thereof is once stored in the register 42 and is then delivered as it is. But if it is negative, the value stored in the register 42 is selected by the selector 43 in accordance with a control input signal Sc, and then the sign thereof is inverted by the subtractor 41, then the thus obtained value being outputted.
In the conventional absolute value arithmetic circuits 10, 20, 30, and 40, when two input signals Sin1 and Sin2 are inputted, the absolute value of a difference between the two signals Sin1 and Sin2, that is, .vertline.sin1-sin2.vertline. is calculated.
However, the conventional absolute value arithmetic circuits 10, 20, 30 and 40 have the following problems:
The parallel-type absolute value arithmetic circuit 10 can compute in short time, or one clock cycle, but requires two computing units 11, 12, thus leading to complicated hardware.
The series type absolute value arithmetic circuit 20 has advantages in view of the scale of the hardware in comparison with that of the absolute value arithmetic circuit 10. However, the process of addition for 2's complement calculation carried out by the sign inverter 22 causes longer computation time. The computation time is substantially twice as long as that of the absolute value computing circuit 10.
With the input register type absolute value arithmetic circuit 30, the scale of the hardware is smaller than that of the absolute value arithmetic circuits 10, 20. However, the computation time requires two clock cycles.
With the output feed-back type absolute value arithmetic circuit 40, the scale of the hardware can be relatively small. However two clock cycles is required for computation.
In the conventional absolute value arithmetic circuits, it has been difficult to miniaturize its circuit size and to satisfy high speed computation.